乘法器是什么意思_乘法器用英语怎么说_乘法器的翻译_乘法器翻译成_乘法器的中文意思_乘法器怎么读,乘法器的读音,乘法器的用法,乘法器的例句

Today very accurate integrated circuit multipliers are available.

目前,非常精确的集成电路乘法器已被采用.

辞典例句

The topology of multiplier, which related with physical implementation closely, also advancedrapidly.

与此同时, 与物理实现紧密相关的乘法器拓扑结构的研究也硕果累累.

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The described multiplier is basedon the variable transconductance principle.

本文叙述一种可变跨导脉冲乘法器.

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And then it compares the LUT method with the multiplier method.

比较了查找表和乘法器两种实现方案.

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This multiplier used modified Booth Algorithm, Wallace tree and 4 - 2 compressor.

乘法器采用改进的Booth算法,简化了部分积符号扩展, 使用Wallace树结构和 4-2 压缩器对部分积归约.

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The circuits of 16 bit adder and 8 bit multiplier are successfully evolved.

采用生长进化方法成功地进化出了16位加法器和8位乘法器.

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The paper analyzed the errors on current balance time division multiplier with active integrator.

研究了电流平衡式有源积分型时分割乘法器.

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Circuit 515 transmits the select signal to a select input of multiplexer 510.

电路515传输选择信号给乘法器510的选择输入端.

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The full custom chip design of 18×18 Modified Booth algorithm and Wallace Tree multiplier is introduced.

本文详细介绍了18×18ModifiedBooth算法和华士树乘法器的全定制芯片设计.

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Multiplexer 510 is controlled by a select signal that is transmitted from circuit 515.

乘法器510是通过从电路515传输过来的选择信号控制的.

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However, the desire for performance computation makes the design of multiplier not come to the end.

但不断提高的高性能运算需求使得高性能乘法器的设计和实现仍然是当前的热门话题.

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Operating at clock speed of 50 MHz in FPGA, the multiplier can meet the demand of DTR.

该乘法器在工作频率为50MHz的FPGA芯片中工作正常, 可以满足光盘的DTR要求.

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In , Newton - Ralphson iterative algorithm , based on the hardware of multiplier, to achieve floating point division operation.

在乘法器的硬件基础上, 通过控制采用Newton-Ralphson迭代算法实现浮点除法运算.

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The Polynomial - Basis Multiplier in the finite field is the key module to realizing ECC basic operations.

有限域上的多项式乘法器是实现ECC底层运算的关键模块.

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A High - speed , Low - power pipelined 16×16 - bit mul - tiplier based on 0.5μ m CMOS Process is designed using Booth encoder , Wallace tree.

提出了一种16×16位的高速低功耗流水线乘法器的设计.

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